Dean Adams
Dr. R Dean Adams has over 20 years experience in patent prosecution, entrepreneurship, management, and engineering. Dean is licensed to practice before the USPTO and has previously driven patent development for one of IBM’s product lines, been Director of IP Strategy for a thousand-person Silicon Valley company, and led a technology startup through successful acquisition. This experience is now used to aid clients in growing their patent portfolios. His strengths in both technology and entrepreneurship are especially appreciated by small companies and startups. In addition to his patent prosecution practice, Dean supports litigation efforts through expert patent analysis and performs patent due diligence on mergers & acquisitions. Dean has authored or co-authored two books and over 20 papers. He is the inventor of over 30 issued patents from his years in development and management. His PhD is from Dartmouth in the area of electrical and computer engineering.
R. Dean Adams, PhD
Licensed Patent Practitioner
Member: American Intellectual Property Law Association
Member: Boston Patent Law Association
Member: National Association of Patent Practitioners.
Member: American Intellectual Property Law Association
Member: Boston Patent Law Association
Member: National Association of Patent Practitioners.
Education
- Doctor of Philosophy in electrical & computer engineering, Dartmouth College, Thayer School of Engineering, 1998
- Master of Engineering Management (includes cross-section of MBA curriculum taught by Tuck School of Business faculty), Dartmouth College, Thayer School of Engineering, 1998
- Master of Science in computer engineering, Dartmouth College, Thayer School of Engineering, 1996
- Bachelor of Science in Electrical Engineering, University of Rhode Island
Papers, Tutorials, & Conference Presentations (Over 40)
- “Patenting & Entrepreneurship for the Test Industry,” seminar, IEEE North Atlantic Test Workshop, May 2018
- “Judicious Patenting: The Lifeblood of Technology Entrepreneurship,” panelist, IEEE North Atlantic Test Workshop, May 2010
- “Process Variation: The Line Blurs,” panelist, IEEE North Atlantic Test Workshop, May 2009
- Embedded Memory Diagnosis and Characterization session chair, International Test Conference, Oct. 2008 (other session chair occurrences too numerous to mention and not included below)
- “Memory Test and Self-Test for Deep-Submicron Technologies,” IEEE Asian Test Symposium Tutorial, Nov. 2006
- “Memory Test and Self-Test for Deep-Submicron Technologies,” IEEE Latin American Test Workshop Tutorial, Mar. 2006
- “Embedded SRAM Design for Testability” Forum Presentation, IEEE International Solid-State Circuits Conference, Feb. 2006
- “Memory Test and Self-Test for Deep-Submicron Technologies,” International Test Conference Tutorial, Nov. 2005
- “Process Variations in the Nanometer Era,” panelist, IEEE International Test Synthesis Workshop, Apr. 2005
- “Memory Test and Self-Test for Deep-Submicron Technologies,” International Test Conference Tutorial, Oct. 2004
- “An Integrated Memory Self Test and EDA Solution,” IEEE Memory Technology, Design, and Test Workshop, Aug. 2004, pp. 92-5
- “Memory Redundancy and Built-In Self Repair,” IEEE Memory Technology, Design, and Test Workshop Embedded Tutorial, Aug. 2004
- “Memory Test and Self-Test for Deep-Submicron Technologies,” VLSI Test Symposium Tutorial, Apr. 2004
- “Practical Memory BIST Analysis and Implementation,” International Test Conference Tutorial, Sept. 2003
- “Optimizing Memory Self Test for Defects,” International Test Conference Tutorial, Oct. 2002
- “Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch,” IEEE Memory Technology, Design, and Test Workshop 2002, pp. 83-7
- “Bitline Contacts in High-Density SRAMS: Design for Testability and Stressability,” International Test Conference 2001, pp. 776-82
- “Defect Analysis And A New Fault Model For Multi-Port SRAMs,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2001
- “Defect Analysis and Realistic Fault Model Extensions for Multi-port SRAMs,” IEEE North Atlantic Test Workshop, May 2001
- “Memory Self Test Utilizing Design Factors,” International Test Conference Tutorial, Oct. 2000
- “Self Test Architecture for Testing Complex Memory Structures,” International Test Conference 2000, pp. 547-56
- “Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories,” IEEE Memory Technology, Design, and Test Workshop 2000, pp. 119-124
- “Test Strategy and March Test Algorithms for Testing Complex Memory Structures,” IEEE North Atlantic Test Workshop, May 2000, pp. 38-43
- “Memory Testing and SOI Technology,” IEEE North Atlantic Test Workshop Tutorial, May 2000
- “Silicon On Insulator Technology Impacts on SRAM Testing,” VLSI Test Symposium 2000, pp. 43-47
- “System On a Chip Testing,” Custom Integrated Circuits Symposium Tutorial, May 1999
- “The Limits of Digital Testing for Dynamic Circuits,” VLSI Test Symposium 1999, pp. 28-32
- “Quad DCVS Dynamic Logic Fault Modeling and Testing,” International Test Conference 1998, pp. 356-62
- “Fault Modeling Analysis Methodology Illustrated with a Dynamic Logic Circuit,” IEEE North Atlantic Test Workshop 1998, pp. 1-5
- “Toward the One-Gigahertz PC: The Design and Test challenges,” Distinguished Fellow Lecture, Dartmouth/Thayer, May 21, 1998
- “Testing Advanced Dynamic Logic,” VLSI Test Symposium Tutorial, Apr. 1998
- “Quad DCVS: A Dynamic Differential Logic Family with Precharge Low and High I/O,” Second IEEE International Caracas Conference on Devices, Circuits, and Systems 1998, pp. 142-5
- “A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal,” International Test Conference 1997, pp. 217-25
- “False Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs,” IEEE Memory Design, Technology, and Test Workshop 1997, pp. 27-32
- “A 5 nanosecond Store Barrier Cache with Dynamic Prediction of Load / Store Conflicts in Superscalar Processors,” IEEE International Solid-State Circuits Conference 1997, pp. 414-5
- “Analysis of a Deceptive Destructive Read Memory Fault Model and Recommended Testing,” IEEE North Atlantic Test Workshop, May 30, 1996
- “Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem,” International Test Conference 1995, pp. 33-44
- “A 370-M Hz Memory Built-In Self-Test State Machine,” European Design and Test Conference 1995, pp. 139-41
- “A 576K 3.5-ns Access BiCMOS ECL Static RAM with Array Built-In Self-Test,” IEEE J. Solid-State Circuits, Vol. 27, No 4, Apr. 1992, pp. 649-56
- “A Flexible and Adaptable SRAM Array Built-In Self-Test Design,” IEEE Design for Testability Workshop Apr. 1992, presentation
- “A 576K 3.5 ns Access BiCMOS ECL Static RAM with Array Built-In Self-Test,” VLSI Circuits Symposium 1991
- “An 11-ns 8Kx18 CMOS Static RAM with 0.5-um Devices,” IEEE J. Solid-State Circuits, Vol. 23, No. 5, Oct. 1988, pp. 1095-1103
- “An 11-ns 8Kx18 CMOS Static RAM,” IEEE International Solid-State Circuits Conference 1988, pp. 242-3
Books
- High Performance Memory Testing: Design Principles, Fault modeling, and Self-Test, R.D. Adams, Kluwer 2002
- Advances in Electronic Testing: Challenges and Methodologies, ed. D. Gizopoulos, (authored chapter on Embedded Memory Testing), Springer 2005
Patents (Over 30 Patents Issued)
- “Testing of ECC memories,” U.S. Pat. No. 7,308,621, Dec. 11, 2007
- “Asynchronous control of memory self test,” U.S. Pat. No. 7,203,873, Apr. 10, 2007
- “Programmable multi-port memory BIST with compact microcode,” U.S. Pat. No. 7,168,005, Jan. 23, 2007
- “Optimized ECC/redundancy fault recovery,” U.S. Pat. No. 7,149,941, Dec. 12, 2006
- “Method and apparatus for testing multi-port memories,” U.S. Pat. No. 7,032,144, Apr. 18, 2006
- “Two-dimensional redundancy calculation,” U.S. Pat. No. 7,003,704, Feb. 21, 2006
- “Built-in self test system and method for two-dimensional memory redundancy allocation,” U.S. Pat. No. 6,907,554, June 14, 2005
- “System initialization of microcode-based memory built-in self-test,” U.S. Pat. No. 6,874,111, Mar. 29, 2005
- “Built-in self test system and method for two-dimensional memory redundancy allocation,” U.S. Pat. No. 6,907,554, Nov. 11, 2004
- “Method and apparatus for testing memory cells for data retention faults,” U.S. Pat. No. 6,681,350, Jan. 20, 2004
- “Programmable memory built-in self-test combining microcode and finite state machine self-test,” U.S. Pat. No. 6,651,201, Nov. 18, 2003
- “Method and apparatus for testing multiport memories,” U.S. Pat. No. 6,557,127, Apr. 29, 2003
- “Testing method for dynamic logic keeper device,” U.S. Pat. No. 6,269,461, July 31, 2001
- “Fault identification by voltage potential signature,” U.S. Pat. No. 6,252,417, June 26, 2001
- “Semiconductor memory device having resistive bitline contact testing,” U.S. Pat. No. 6,208,572, Mar. 27, 2001
- “Method and apparatus for testing dynamic logic using an improved reset pulse,” U.S. Pat. No. 6,181,155, Jan. 30, 2001
- “On-chip test circuit for evaluating an on-chip signal using an external test signal,” U.S. Pat. No. 6,163,862, Dec. 19, 2000
- “Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure,” U.S. Pat. No. 5,912,901, June 15, 1999
- “Testing associative memory,” U.S. Pat. No. 5,802,070, Sept. 1, 1998
- “Memory array built-in self-test circuit for testing multi-port memory arrays,” U.S. Pat. No. 5,796,745, Aug. 18, 1998
- “Dynamic dielectric protection circuit for a receiver,” U.S. Pat. No. 5,793,592, Aug. 11, 1998
- “Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor,” U.S.Pat. No. 5,790,564, Aug. 4, 1998
- “Test coverage of embedded memories on semiconductor substrates,” U.S. Pat. No. 5,784,323, July 21, 1998
- “Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor,” U.S.Pat. No. 5,771,242, June 23, 1998
- “Method and apparatus to determine erroneous value in memory cells using data compression,” U.S. Pat. No. 5,761,213, June 2, 1998
- “Rapid compare of two binary numbers,” U.S. Pat. No. 5,745,498, Apr. 28, 1998
- “Using one memory to supply addresses to an associated memory during testing,” U.S. Pat. No. 5,563,833, October 8, 1996, Pat. No. 5,740,098, Apr. 14, 1998
- “High speed greater than or equal to compare circuit,” U.S. Pat. No. 5,592,142, Jan. 7, 1997
- “BIST Tester for multiple memories,” U.S. Pat. No. 5,535,164, July 9, 1996
- “Module level electronic redundancy,” U.S. Pat. No. 5,313,424, May 17, 1994
- “CMOS Off-chip driver circuits,” U.S. Pat. No. 4,782,250, Nov. 1, 1988
Timothy Dell
Timothy Dell is an experienced patent practitioner with a track record of over 25 years in technology development and is inventor of 89 U.S. patents generated while working in the electronics industry. He is licensed to practice before the USPTO and was a Master Inventor at IBM, which included supporting patent prosecution, patent evaluation, patent mining, and managing one of IBM’s patent portfolios for product development. Tim supports clients through his deep understanding of technology and a desire to help obtain high-quality patents. Tim has authored numerous technical articles and conference presentations. He received BEEE and MEEE degrees from Rensselaer Polytechnic Institute. He is a Senior Member of the Institute of Electrical and Electronic Engineers and a member of the National Association of Patent Practitioners.
Education
- Master of Engineering, Rensselaer Polytechnic Institute
- Bachelor of Engineering in Electrical Engineering, Rensselaer Polytechnic Institute
Publications
- "IBM System z10 design for RAS," IBM Journal of Research and Development, Vol. 53, No. 1, Jan. 2009, pp. 11-1
- "System RAS Implications of DRAM Soft Errors," IBM Journal of Research and Development, Vol. 52, No. 3, May 2008, pp. 307-14
- "Memory Extended Runtime Supplier Qualification," IBM Academy of Technology Conference on System Test 2008
- "The RAS Implications of DIMM Connector Failure Rates in Large, Highly Available Server Systems," IEEE 53rd Holm Conference on Electrical Contacts 2007
- "ECC vs. CRC in High-speed Computer Buses," IEEE High Performance Computer Reliability Workshop 2006
- "The Use of ECC Technology in Protecting Against High-Speed Bus Packaging Failures," Electronic Packaging Symposium (Invited Paper) 2003
- "Embedded DRAM Application Tradeoffs," DesignCon2K 2000
- "On-chip System Core Integration Techniques," DesignCon99 1999
- "Fault-tolerant Memory Subsystems for PC-based Servers," DesignCon98 1998
- "Memory Card Integrated Design Services," IBM MicroNews 1998
- "The New Challenges of Memory Subsystem Design," DesignCon97 1997, HP Test Equipment World Tour Award
- "Concurrent Support of FPM, EDO and Synchronous DRAM," IBM MicroNews, Best Paper Award 1997
- "ECC-on-SIMM Test Challenges," ITC'94 Proceedings of the 1994 international conference on Test, pp. 511-15
Patents (89 Patents Issued)
- “Selective error coding,” U.S. Pat. No. 9,858,145, Jan. 2, 2018
- “Bank-level fault management in a memory system,” U.S. Pat. No. 9,857,993, Jan. 2, 2018
- “Selective error coding,” U.S. Pat. No. 9,703,630, Jul. 11, 2017
- “Memory data security,” U.S. Pat. No. 9,606,939, Mar. 28, 2017
- “Bank-level fault management in a memory system,” U.S. Pat. No. 9,600,189, Mar. 21, 2017
- “Virtual grouping of memory,” U.S. Pat. No. 9,600,187, Mar. 21, 2017
- “Traffic and temperature based memory testing,” U.S. Pat. No. 9,576,682, Feb. 21, 2017
- “Memory data security,” U.S. Pat. No. 9,575,904, Feb. 21, 2017
- “Traffic and temperature based memory testing,” U.S. Pat. No. 9,570,199, Feb. 14, 2017
- “Performance optimization of read functions in a memory system,” U.S. Pat. No. 9,547,449, Jan. 17, 2017
- “Performance optimization of read functions in a memory system,” U.S. Pat. No. 9,542,110, Jan. 10, 2017
- “Self monitoring and self repairing ECC,” U.S. Pat. No. 9,535,784, Jan. 3, 2017
- “Implementing memory performance management and enhanced memory reliability accounting for thermal conditions,” U.S. Pat. No. 9,442,816, Sep. 13, 2016
- “Implementing enhanced security with storing data in DRAMs,” U.S. Pat. No. 9,342,700, May 17, 2016
- “Implementing enhanced security with storing data in DRAMs,” U.S. Pat. No. 9,336,401, May 10, 2016
- “Performance management of subsystems in a server by effective usage of resources,” U.S. Pat. No. 9,329,648, May 3, 2016
- “Implementing ECC redundancy using reconfigurable logic blocks,” U.S. Pat. No. 9,230,687, Jan. 5, 2016
- “Memory operation of paired memory devices,” U.S. Pat. No. 9,147,499, Sep. 29, 2015
- “Memory margin management,” U.S. Pat. No. 9,087,615, Jul. 21, 2015
- “Memory data management,” U.S. Pat. No. 9,043,569, May 26, 2015
- “Implementing DRAM failure scenarios mitigation by using buffer techniques delaying usage of RAS features in computer systems,” U.S. Pat. No. 9,015,522, Apr. 21, 2015
- “Self monitoring and self repairing ECC,” U.S. Pat. No. 8,996,953, Mar. 31, 2015
- “Memory operation of paired memory devices,” U.S. Pat. No. 8,996,935, Mar. 31, 2015
- “Memory operation upon failure of one of two paired memory devices,” U.S. Pat. No. 8,964,495, Feb. 24, 2015
- “Memory operation upon failure of one of two paired memory devices,” U.S. Pat. No. 8,848,470, Sep. 30, 2014
- “System, method and storage medium for providing fault detection and correction in a memory subsystem,” U.S. Pat. No. 8,589,769, Nov. 19, 2013
- “Providing a memory device having a shared error feedback pin,” U.S. Pat. No. 8,359,521, Jan. 22, 2013
- “Cascade interconnect memory system with enhanced reliability,” U.S. Pat. No. 8,245,105, Aug. 14, 2012
- “Cyclical redundancy code for use in a high-speed serial link,” U.S. Pat. No. 8,201,069, Jun. 12, 2012
- “System to improve error code decoding using historical information and associated methods,” U.S. Pat. No. 8,185,801, May 22, 2012
- “System to improve miscorrection rates in error control code through buffering and associated methods,” U.S. Pat. No. 8,176,391, May 8, 2012
- “System to improve memory reliability and associated methods,” U.S. Pat. No. 8,171,377, May 1, 2012
- “System, method and storage medium for providing fault detection and correction in a memory subsystem,” U.S. Pat. No. 8,140,942, Mar. 20, 2012
- “System and method for error correction and detection in a memory system,” U.S. Pat. No. 8,041,990, Oct. 18, 2011
- “System and method for providing a high fault tolerant memory system,” U.S. Pat. No. 8,041,989, Oct. 18, 2011
- “Forward error correction encoding for multiple link transmission compatible with 64B/66B scrambling,” U.S. Pat. No. 7,996,747, Aug. 9, 2011
- “Double DRAM bit steering for multiple error corrections,” U.S. Pat. No. 7,840,860, Nov. 23, 2010
- “Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code,” U.S. Pat. No. 7,721,178, May 18, 2010
- “Systems and methods for improving serviceability of a memory system,” U.S. Pat. No. 7,721,140, May 18, 2010
- “Systems, methods and computer program products for utilizing a spare lane for additional checkbits,” U.S. Pat. No. 7,712,010, May 4, 2010
- “System, method and storage medium for providing segment level sparing,” U.S. Pat. No. 7,539,800, May 26, 2009
- “Double DRAM bit steering for multiple error corrections,” U.S. Pat. No. 7,523,364, Apr. 21, 2009
- “System, method and storage medium for providing fault detection and correction in a memory subsystem,” U.S. Pat. No. 7,484,161, Jan 27, 2009
- “System, method and storage medium for providing fault detection and correction in a memory subsystem,” U.S. Pat. No. 7,331,010, Feb. 12, 2008
- “Dynamically replacing a failed chip,” U.S. Pat. No. 6,567,950, May 20, 20030
- “Method and apparatus for addressing individual banks of DRAMs on a memory card,” U.S. Pat. No. 6,467,018, Oct. 15, 2002
- “Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket,” U.S. Pat. No. 6,457,155, Sep. 24, 2002
- “Address re-mapping for memory module using presence detect data,” U.S. Pat. No. 6,446,184, Sep. 3, 2002
- “Highspeed extendable bus architecture,” U.S. Pat. No. 6,445,744, Sep. 3, 2002
- “Apparatus and method for modifying signals from a CPU to a memory card,” U.S. Pat. No. 6,408,356, Jun. 18, 2002
- “Memory card utilizing two wire bus,” U.S. Pat. No. 6,385,685, May 7, 2002
- “Dynamic configuration of memory module using presence detect data,” U.S. Pat. No. 6,381,685, Apr. 30, 2002
- “On-board scrubbing of soft errors memory module,” U.S. Pat. No. 6,349,390,, Feb. 19, 2002
- “Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures,” U.S. Pat. No. 6,347,367, Feb. 12, 2002
- “Power management on a memory card having a signal processing element,” U.S. Pat. No. 6,327,664, Dec. 4, 2001
- “Memory card utilizing two wire bus,” U.S. Pat. No. 6,233,639, May 15, 2001
- “Address re-mapping for memory module using presence detect data,” U.S. Pat. No. 6,209,074, Mar. 27, 2001
- “Memory card design with parity and ECC for non-parity and non-ECC systems,” U.S. Pat. No. 6,185,718, Feb. 6, 2001
- “High bandwidth DRAM with low operating power modes,” U.S. Pat. No. 6,178,517, Jan. 23, 2001
- “Dynamic configuration of memory module using modified presence detect data,” U.S. Pat. No. 6,173,382, Jan. 9, 2001
- “Clock distribution system for synchronous circuit assemblies,” U.S. Pat. No. 6,130,475, Oct. 10, 2000
- “Self-initiated self-refresh mode for memory modules,” U.S. Pat. No. 6,118,719, Sep. 12, 2000
- “SIMM/DIMM memory module,” U.S. Pat. No. 6,111,757, Aug. 29, 2000
- “Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket,” U.S. Pat. No. 6,108,730, Aug. 22, 2000
- “Dual state memory card having combined and single circuit operation,” U.S. Pat. No. 6,097,883, Aug. 1, 2000
- “Dynamically configurable memory adapter using electronic presence detects,” U.S. Pat. No. 6,092,146, Jul. 18, 2000
- “Reconfigurable I/O DRAM,” U.S. Pat. No. 6,070,262, May 30, 2000
- “Error protection power-on-self-test for memory cards having ECC on board,” U.S. Pat. No. 6,070,255,, May 30, 2000
- “High bandwidth narrow I/O memory device with command stacking,” U.S. Pat. No. 6,065,093, May 16, 2000
- “Method and apparatus for ECC bus protection in a computer system with non-parity memory,” U.S. Pat. No. 6,052,818, Apr. 18, 2000
- “Error propagation operating mode for error correcting code retrofit apparatus,” U.S. Pat. No. 6,044,483, Mar. 28, 2000
- “Human sensorially significant sequential error event notification for an ECC system,” U.S. Pat. No. 6,044,479, Mar. 28, 2000
- “Method for modifying signals received by memory cards RAS signals as address lines,” U.S. Pat. No. 6,035,370, Mar. 7, 2000
- “Error correcting code retrofit method and apparatus for multiple memory configurations,” U.S. Pat. No. 6,018,817, Jan. 25, 2000
- “Error correcting code retrofit method and apparatus for multiple memory configurations,” U.S. Pat. No. 6,009,548, Dec. 18, 1999
- “Dynamic redundancy for random access memory assemblies,” U.S. Pat. No. 5,996,096, Nov. 30, 1999
- “Stackable memory card,” U.S. Pat. No. 5,963,464, Oct. 5, 1999
- “High density SIMM or DIMM with RAS address re-mapping,” U.S. Pat. No. 5,926,827, Jul. 20, 1999
- “Input port switching protocol for a random access memory,” U.S. Pat. No. 5,898,623, Apr. 27, 1999
- “Programmable burst length DRAM,” U.S. Pat. No. 5,896,404, Apr. 20, 1999
- “High speed and low cost SDRAM memory subsystem,” U.S. Pat. No. 5,896,346, Apr. 20, 1999
- “Method of detecting error correction devices on plug-compatible memory modules,” U.S. Pat. No. 5,881,072, Mar. 9, 1999
- “Technique for converting system signals from one address configuration to a different address configuration,” U.S. Pat. No. 5,745,914, Apr. 28, 1998
- “Method and structure for providing error correction code within a system having SIMMs,” U.S. Pat. No. 5,623,506, Apr. 22, 1997
- “Method and structure for providing automatic parity sensing,” U.S. Pat. No. 5,541,941, Jul 30, 1996
- “Synchronous memory packaged in single/dual in-line memory module and method of fabrication,” U.S. Pat. No. 5,513,135, Apr. 30, 1996
- “Method and structure for providing error correction code and automatic parity sensing,” U.S. Pat. No. 5,465,262, Nov. 7, 1995
- “Method and structure for providing error correction code for each byte on SIMM'S,” U.S. Pat. No. 5,450,422, Sep. 12, 1995
- “Method and structure for providing error correction code and parity for each byte on SIMM's,” U.S. Pat. No. 5,379,304, Jan. 3, 1995
Dave Appenzeller
Dave Appenzeller has 20 years of experience in engineering, executive management, and patent prosecution. Leading a 200+ person international team, Dave was responsible for the development, production, and enablement of numerous IBM high performance, high volume microprocessors. His clients included Apple, Nintendo, IBM servers and other high end embedded customers. Small companies and startups appreciate the scope of Dave’s skills, spanning ISA development, design, verification, test, cost reduction, and manufacturing. Dave is member of the patent bar, the National Association of Patent Practitioners, and the Boston Intellectual Property Law Association.
Education
- MBA in Advanced Management, Champlain College, Summa Cum Laude, 2020
- Harvard University Executive Leadership Training, 1999
- BSEE in Electrical and Computer Engineering, Drexel University, Magna Cum Laude, 1993
Patents & Publications
- A Low-Power RISC microprocessor using dual PLLs in a 0.13um SOI Technology with Copper Interconnect and Low-K BEOL Dielectric, Geissler, et al. International Solid-State Circuits Conference, 2003
- PowerPC 970 in 130nm and 90nm Technologies, Rohrer et al., International Solid-State Circuits Conference, 2002
- BOA: The Architecture of a Binary Translation Processor, Altman et. al., Binary Translation Workshop, 1998
- Integrated Circuit Chip and Pass Gate Logic Family Therefor, Appenzeller et al., Patent #5,508,641, 1996
- Formal Verification of a PowerPC Microprocessor, Appenzeller, et al., IEEE Conf. on Computer Design, 1995